Topic: SuperCPU128 programming without SuperRAM

[MIRKOSOFT]

Hi!


I have SuperCPU128 without SuperRAM, daughtercard is missing, SIMMs modules I have two 16MB.


My Q is very simple:


CAN BE USED OPCODES OF WDC65816 CPU AND ITS NATIVE MODE ALSO IF IS SUPERRAM 0MB?


Why Q, not test...?


I have many compilers of WDC65816, I tried to create simple program which switches btw. SCPU NATIVE and EMULATE mode.


Program was compiled succesfully, but after starting on C128DCR with SCPU128 0MB RAM system crashes...


So, I don't know if I did something wrong in using opcodes or system crashes 'cause SCPU has 0MB RAM...?


Also, is possible to use any features (e.g. SuperRAM or speed) of SCPU64 in C128 mode?


Many thanks for explaining the problem.


Miro

[Pihti]

Hi!

I saw your question and as I know how to use the 65816 in native mode, I decided to answer.

The system does not need any superram to be able to run native mode code. But there is many things you need to take account if you want to use the native mode:

1. The kernal interrupt routines do not understand shit about 65816 native mode. They need to be patched if you want to use them.
2. The interrupt vectors are different with 65816 native and emulation mode. On emulation mode, the system works exactly like standard 6502 interrupts work and the vectors are same. But on 65816, the vectors CHANGE when you switch to emulation mode! On standard c64/128 those addresses point to wrong locations. You need to disable ROM to be able to write new vectors to ram and then disable ROM, then change to native mode.

So, to be able to use the native mode, better make own interrupt vectors and disable rom chips. If you just want to try how the native commands feel, just use these commands:

SEI
CLC
XEC


and last
SEC
XEC
CLI


I have used this technique to be able to run native code on my supercpu. It works flawlessly, but remember! If you have roms on and press RESTORE while running native code, you will crash!

Best Regards,
Pekka Takala

[Wagner]

1. The kernal interrupt routines do not understand shit about 65816 native mode. They need to be patched if you want to use them.

That's not true.  Try the following:

Code: [Select]

LDA #$0E
STA $FF00
CLC
XCE

;native code goes here

SEC
XCE
RTS
As long as the Kernal is banked in, interrupts during native mode still work normally.

If you have roms on and press RESTORE while running native code, you will crash!

Again, not true.  Both maskable and nonmaskable interrupts work just fine. 

[Pihti]

Do you actually own a supercpu? If your code works, then you have not gotten any irq's during the code. It is pretty easy to make code so fast that it wont get a interrupt while executing.

http://www.westerndesigncenter.com/wdc/datasheets/Programmanual.pdf <--- This is the programming manual for 65816, 6502 and 65c02.

Read from page 44 onwards. Especially, read things about interrupts.

On page 55, you can see the vector table of 6502 and 65816. When you compare them, you can see that in emulation mode the system looks like a 6502 system, and that is why supercpu can work normally with c64 and c128 code. From boot it is in emulation mode and most of the new commands are there usable also, except that they cannot be in 16 bit mode.

When you put the native mode on the irq vector points to $ffee-$ffef, nmi to $ffea-$ffeb, brk has its own vector at $ffe6-$ffe7 and so on.

On c128 page 15 the vectors from fff0-ffff show:

RESET  $ff3d
IRQ/BRK $ff17
NMI $ff05

If on 65816 native mode:
IRQ points to $c00f
nmi points to $f84c
and brk to $6c03

On native mode, irq would jump to $c00f. There is jmp $cc5b.
There is a routine that ends to an PLA/RTS, that definitely will not work correctly with irq's.

if nmi is pressed, the pointer goes to $f84c and there is not correct code. Needless to say, $6c03 propably will not work correctly.

So you must take the interrupts into account or disable them before running any commands using 65816 native mode. The KERNAL rom does not have correct code for 65816 native mode!

Yes, it is possible to use 65816 native mode interrupts. I do not say that they do not work, but you must do the code by yourself because the 6502 code kernal rom does not even know about 16 bit code.

When the system gets a interrupt, if it is on emulation mode everything goes fine. On native mode, you must take account that the accu and indexes length can vary. On usual 65816 interrupt routine the routine looks like this:

* begin
   pha
   phx
   phy
   php
   phd
   phb
   pea $0000
   pld
   pea $0000
   plb
   plb
*set the length of accu and indexes
*accept the interrupt source
*code

  plb
  pld
  plp  ;to get the correct length of index and accu
  ply
  plx
  pla
  rti

I have done this, so I know what I am speaking about.

[MIRKOSOFT]

Hi!

Many thanks for every reply.

Currently I own SuperCPU128 with 16MB SuperRAM.

Also I need to know programming SCPU without SuperRAM 'cause OS which we are creating ACE128TOS will have two editions:

8-bit: native mode 8502, if SuperCPU available uses its speed, if SuperRAM available, uses it as RAM expansion.

16-bit: native mode 65816, SuperCPU required, if SCPU has SuperRAM is in use, if is SuperRAM missing, uses standard C128 RAM & its expansions...

In both editions is possible to allow Disk Swapping... so, no everytime is needed RAM expansion/SuperRAM

I will watching this topic as long as I'll need... and thanks to everybody which can help.

Miro

[Wagner]

Do you actually own a supercpu?

Of course.

I understand what you're saying, but interrupts in native mode are handled differently, than in emulation mode.  But rather than taking my word for it, I will quote from an article written by Mark Fellows--the SuperCPU designer.

"Implementing the additional 65C816 interrupt vector locations was a challenge during the design of the SuperCPU.  Upon examination, you will find that all the Native mode vectors...are located within the Kernal Jump Table!  At first glance this seems to preclude the use of Native interrupts...while the Kernal ROM is in context.  Luckily, the 65C816's designers may have forseen such a circumstance and have provided the VPB signal which, when asserted, indicates when a vector fetch is taking place.  The SuperCPU PLD decodes VPB and can remap memory so that the vectors are fetched from a table in another location.

Although the problem of accessing the additional vectors was solved, there were still some issues regarding compatibility with the C64/128 operating system that had to be addressed.  In order to guarantee 100% compatibility with existing Commodore programs, the existing IRQ/BRK and NMI vectors and interrupt routines had to be duplicated exactly.  This was no problem because the 65C816 in Emulation mode will execute the existing Kernal interrupt routines properly.

With the compatibility issue solved we moved on to the next problem--how to provide enhanced interrupt services in the Kernal for the 65C816 Native mode and for situations where an Emulation mode interrupt occurs when the SuperCPU hardware registers have been enabled.  To solve these problems a second vector table was added that is accessed when [in Native mode].

Note: When the Kernal ROM is switched out, the vectors are accessed from the RAM 'under' the Kernal ROM.  As on the C64, the programmer in this case must provide his own vector table and interrupt service routines.

With new SuperCPU programs, a problem arises when the Kernal must service an interrupt that is generated while the 65C816 is in Native mode.  To solve the problem, the Native mode interrupt service routines in the SuperCPU Kernal first save the 16-bit register values on the stack along with a re-entry address and then switch the 65C816 to Emulation mode.  Control is then passed to the enhanced Emulation mode interrupt routines which perform the interrupt processing.  When interrupt processing has finished, the re-entry routine switches the processor back to Native mode and restores the 16-bit registers.

Handling Native interrupts in this manner makes it easy for programmers to write new software for the SuperCPU that takes advantage of the 16-bit registers and other advanced features of the 65C816.  Unless the Kernal ROM is switched out, programmers do not need to include any interrupt handlers to provide special service to interrupts that occur while the 65C816 is in Native mode.  In addition, because the Kernal takes care of the switching from Native to Emulation mode, existing custom interrupt handlers do not have to be re-written and can be used as-is by linking into the standard Kernal redirection vectors at $0314-$0319."

So you must take the interrupts into account or disable them before running any commands using 65816 native mode. The KERNAL rom does not have correct code for 65816 native mode!

Still doubting?  How about some code?

Code: [Select]


   * = $2000

   lda #$0e
   sta $ff00 ;Kernal and IO bank

   clc
   xce ;native mode
   rep #$10 ;index registers 16-bits
   .rl
   stz $d020
   stz $d021
   lda $d011
   and #$f7
   sta d011 ;24 row screen

g5 lda #$fb
g3 inc $a2
   cmp $d012 ;wait for raster to go offscreen
   bne g3

   lda d011
   dec a
   cmp #$10
   bcs g4 ;take branch if scrolling one pixel
   lda #$17 ;reset fine vertical scroll to bottom
g4 sta d011
   sta $d011
   bcs g8

   rep #$30 ;accumulator also 16-bits
   .al
   ldx #$428 ;screen row 2 source block move address
   ldy #$400 ;screen row 1 destination block move address
   lda #1000-40-1 ;960 bytes to move
   mvn 0,0
   ldx #$d828 ;color source
   ldy #$d800 ;color destination
   lda #1000-40-1 ;another 960 bytes to move
   mvn 0,0

   clc
   ldx #38
g1 lda $a1
   sta $dbc0,x ;put something into row 25 of color RAM
   rol
   eor $a1
   sta $7c0,x ;put something into row 25 of screen
   dex
   dex
   bpl g1

   sep #$20 ;accumulator back to 8-bits
  .as
g8 lda #$fb
g6 cmp $d012 ;for the non-MVN 0,0 case
   beq g6

   lda $dc01
   bmi g5 ;go back if STOP key not pressed

   lda #$1b
   sta $d011 ;reset VIC register
   sec
   xce ;return to emulation mode
   .rs
   rts

d011
   byt $17

Execute the attached file with BLOAD"scroll.816",u8 and then SYS8192.